Two Hypervisors, One SoC: Replacing Hafnium with 30K Lines of Rust

It sounds like you've encountered some interesting challenges while working with ARM's physical address space split and cache coherency issues during your development of the Security Partition Manager (SPMC). Let’s break down each issue and how it was resolved:

The Silent SIMD Trap

Issue: The SPMC hangs on the first read_volatile call in debug mode, but not in release mode. No fault or output is generated.

Root Cause:

• Rust's debug-mode codegen emits NEON instructions for certain operations.
• TF-A’s default configuration traps all floating-point and SIMD instructions at EL3.
• The trap handler wasn’t prepared to handle this type of exception, leading to an infinite loop in the EL3 handler.

Solution:

• Enable CTX_INCLUDE_FPREGS=1 to include FP/SIMD registers in the context switch. This ensures that NEON instructions are properly handled and don't cause traps at EL3.

The NS Bit and the Invisible Write

Issue: The SPMC writes SP descriptors to a buffer, but pKVM reads back zeros instead of the expected data.

Root Cause:

• ARM has two physical address spaces (Secure and Non-Secure).

Read the full article at DEV Community

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